1. Technical Field of the Invention
This invention relates generally to data communications and more particularly to data communications via devices operating at different rates.
2. Description of Related Art
As is known, a receiver is operable to detect binary data received via a serial data bus and to convert the data from a higher speed serial form to a lower speed parallel form such that it can be further processed and/or manipulated at lower speeds. For example, a receiver might detect and convert 16 bits of incoming serial data at 10 gigabits-per-second (Gbps) to a 16-bit parallel word having a rate of 1/16th of 10 GHz.
As is also known, one type of receiver includes a clock and data recovery (CDR) stage followed by a shift register. The CDR functions to recover a clock signal and the data from the incoming serial data. In particular, the CDR includes an oscillator that locks to the incoming bit stream such that it produces the recovered clock having a frequency equal to the rate of the incoming serial data. The recovered clock is then used to detect, and hence recover, each bit of the incoming serial data. As each bit is detected, it is clocked into the shift register. When the shift register contains a next full data word (e.g., a parallel data word), the receiver outputs the parallel data word.
As is further known, a CDR will generally operate in two modes: a startup mode and a normal mode. In the startup mode, the oscillator of the CDR produces a fixed clock that is a multiple of a stable reference clock. The rate of the fixed clock is equal to (with some tolerance) the rate of the incoming serial data, but is not synchronous with the clocking of the incoming stream of data. The CDR is in this mode when the receiver is enabled and/or anytime synchronization between the recovered clock and the clocking of the incoming data is lost. The CDR enters the normal mode when synchronization between the recovered clock and the clocking of the incoming serial data is achieved.
Typically, to effectively recover high speed serial data (e.g., greater than 1 Gbps), a CDR is implemented using analog components due to the oscillator. In particular, to produce a clock having a very high adjustable frequency, analog oscillators are currently the practical choice for a one sample per bit receiver. While analog oscillators are the oscillators of choice, their maximum rate and/or bandwidth is limited by the particular semiconductor process and circuit used to implement the receiver.
As is even further known, a receiver is often required to detect multiple serial data rates. One approach to solving this issue is to use the analog form of a one sample per bit receiver, but vary the CDR so that it is able to track the desired serial rates. But this variation includes problems associated with changing analog circuits. For example, to get different operating frequencies different circuit elements must be switched in and out of the circuit. This becomes very complex if a large number of different oscillator frequencies are targeted with a wide range bandwidth. Further, component values needed at the lowest data rates may be physically large rendering them impractical for use with an integrated circuit, and most oscillators become nonlinear if used at a frequency that is much less than its designed center frequency.
An issue with receivers implemented in the analog domain is drift. As is known, depending on the type of encoding, the serial data stream will typically have regions where there are no transitions from one signal level to the other. This is a well known problem for analog CDRs that require frequent transitions to accurately track the stream of data. If too long of time passes without a transition, the oscillator of the CDR can drift away from the correct phase. As such, the CDR may lose synchronization with the incoming data stream. By keeping the CDR in the startup mode where it referencing the local clock, this drift caused by the source can be reduce, thus leaving drift that is caused by the allowed transmit and receive clocks tolerance.
Another issue with such receivers is received signal impairments where a received signal includes noise and/or distortion caused by the channel, such as inter-symbol interference. In general, this is a high frequency form of distortion that shifts the transitions in the received signal producing jitter. The receiver must remain synchronized to the incoming data stream and perform low pass filtering to reject the high frequency jitter.
Another issue for such receivers is high speed circuit implementations on integrated circuits. For instance, in many data communication/signal processing functions, there is a trade-off between processing sequentially at high speeds versus spatially at lower speeds. Often the lower speed choice results in a net power reduction and the ability to use known circuit implementations that have more reliable results.
Therefore, a need exists for a receiver that is operable to receive data at lower data rates while minimizing the adverse affects of drift, received signal impairments and achieves a desired balance with high speed circuit considerations.